Xiaopeng Zhang (张晓鹏)

Ph.D.

Doctoral education (completed in 2022)

Biography

I received my Ph.D. in 2022 from the Department of Computer Science and Engineering, The Chinese University of Hong Kong (CUHK), under the supervision of Prof. Evangeline F.Y. Young. Previously, I received my bachelor's degree in Software Engineering from Shandong University (SDU) and my master's degree in Computer Science and Technology from Beihang University (BUAA). My research spans physical design and design for manufacturability in VLSI CAD. My doctoral work focused on learning-based layout generation, while my industrial work focuses on routing automation, power integrity analysis for 3D ICs, and advanced packaging.

[J3] Fangzhou Wang, Qijing Wang, Lilas Alrahis, Bangqi Fu, Shui Jiang, Xiaopeng Zhang, Ozgur Sinanoglu, Tsung-Yi Ho, Evangeline F.Y. Young, and Johann Knechtel, “TroLLoc: Security Closure against Hardware Trojans by Logic Locking and Layout Hardening”, Journal of Hardware and Systems Security, vol. 10, article 4, 2026. [paper]

[J2] Bentian Jiang, Jingsong Chen, Jinwei Liu, Lixin Liu, Fangzhou Wang, Xiaopeng Zhang, and Evangeline F.Y. Young, “CU.POKer: Placing DNNs on WSE with Optimal Kernel Sizing and Efﬁcient Protocol Optimization”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 41, no. 6, pp. 1888–1901, 2022. [paper]

[J1] Yong Chen, Hui Zhang, Xiaopeng Zhang, and Rui Liu, “Regularized Semi-Nonnegative Matrix Factorization for Hashing”, IEEE Transactions on Multimedia, 2017. [paper]

[C11] Qijing Wang, Xiaopeng Zhang, Martin D.F. Wong, and Evangeline F.Y. Young, “Controlayout: Conditional diffusion for style-controllable and violation-fixable layout pattern generation”, Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI), 2024.

[C10] Fangzhou Wang, Qijing Wang, Bangqi Fu, Shui Jiang, Xiaopeng Zhang, Lilas Alrahis, Ozgur Sinanoglu, Johann Knechtel, Tsung-Yi Ho, and Evangeline F.Y. Young, “Security closure of IC layouts against hardware Trojans”, ACM International Symposium on Physical Design (ISPD), pp. 229–237, 2023.

[C9] Xiaopeng Zhang, Shoubo Hu, Zhitang Chen, Shengyu Zhu, Evangeline F.Y. Young, Pengyun Li, Cheng Chen, Yu Huang, and Jianye Hao, “RCANet: Root Cause Analysis via Latent Variable Interaction Modeling for Yield Improvement”, IEEE International Test Conference (ITC), pp. 100–107, 2022.

[C8] Jinwei Liu, Xiaopeng Zhang, Shiju Lin, Xinshi Zang, Jingsong Chen, Bentian Jiang, Martin D.F. Wong, and Evangeline F.Y. Young, “Partition and place finite element model on wafer-scale engine”, The 59th Annual Design Automation Conference (DAC), 2022.

[C7] Xiaopeng Zhang, Haoyu Yang and Evangeline F.Y. Young, “Attentional Transfer is All You Need: Technology-aware Layout Pattern Generation”, The 58th Annual Design Automation Conference (DAC), San Francisco, Dec. 5–9, 2021.

[C6] Bentian Jiang, Xiaopeng Zhang, Lixin Liu and Evangeline F.Y. Young, “Building up End-to-end Mask Optimization Framework with Self-training”, ACM International Symposium on Physical Design (ISPD), Virtual Conference, March 21-24, 2021.

[C5] Dan Zheng*, Xiaopeng Zhang*, Chak-Wa Pui, Evangeline F.Y. Young, “Multi-FPGA Co-optimization: Hybrid Routing and Competitive-based Time Division Multiplexing Assignment”, IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Tokyo, Japan, Jan. 18–21, 2021 (* co-first authors).

[C4] Xiaopeng Zhang, James Shiely and Evangeline F.Y. Young, “Layout Pattern Generation and Legalization with Generative Learning Models”, The 39th IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Virtual Conference, Nov. 2–5, 2020. [preprint][slides]

[C3] Bentian Jiang*, Jingsong Chen*, Jinwei Liu, Lixin Liu, Fangzhou Wang, Xiaopeng Zhang, Evangeline F. Y. Young, “CU.POKer: Placing DNNs on Wafer-Scale AI Accelerator with Optimal Kernel Sizing”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Virtual Event, Nov. 2–5, 2020 (* co-first authors).

[C2] Bentian Jiang, Xiaopeng Zhang, Ran Chen, Gengjie Chen, Peishan Tu, Wei Li, Evangeline F.Y. Young and Bei Yu, “FIT: Fill Insertion Considering Timing”, The 56th Annual Design Automation Conference (DAC), San Francisco, CA, USA, June 24–29, 2019. [paper]

[C1] Xiaopeng Zhang, Hui Zhang, Yong Chen, and Xianglong Liu, “Large-Margin Supervised Hashing”, International Conference on Neural Information Processing (ICONIP), 2017. [paper]

Second Place Award at Contest on “Wafer-Scale Physics Modeling”	ISPD	2021
First Place Award at Contest on “Wafer-Scale Deep Learning Accelerator Placement”	ISPD	2020
Third Place Award at Contest on “System-level FPGA Routing with Timing Division Multiplexing Technique”	ICCAD	2019
Second Place Award at Contest on “Timing-aware Dummy Fill Insertion”	ICCAD	2018
Full Postgraduate Studentship	CUHK	2018 - 2022
National Scholarship	BUAA	2017

Principal Engineer | Huawei HiSilicon
- EDA/CAD tool development for custom layout and routing automation, power integrity analysis for 3D ICs, and advanced packaging.
- October 2022 – October 2026, Shenzhen, China.

Research Intern | Huawei Hong Kong Research Center
- AI-driven root cause analysis using layout-aware scan diagnosis for yield improvement.
- June 2021 – December 2021, Hong Kong SAR, China.